PONCHI AI · SPEC-TO-HARDWARE
AI-assisted engineering for electronics teams. Clear requirements, controlled checks and traceable results.
Our founder's engineering track record
WORKFLOW DESIGN
Power, sensors, interfaces and size.
Turn specs into design tasks.
SPICE simulation, PCB layout and enclosure CAD.
Check results and refine the design.
Assembled boards, sensors and enclosures.
AI models: Anthropic · OpenAI
SOLUTIONS
Spec-to-Hardware is our initial focus, with Spec-to-ASIC as a complementary direction. Both are in development. The images below illustrate our founder's engineering experience; the local requirements example shows the narrower work implemented by Ponchi AI.
Our initial focus is requirements analysis, tool-based checks and traceable reports for electronics teams. A local development example checks explicit numeric bounds and keeps unresolved values visible.
Inspect the requirements example
We are developing workflows from functional and performance requirements to circuit architecture, schematics or RTL, and simulation results, with engineers reviewing each design decision and its checks.
Explore founder ASIC design work
SPEC-TO-ASIC
Explore our founder’s UltraSense mixed-signal ASICs and the wider chip portfolio behind them. Sensor interfaces, high-voltage drive, control and sensing algorithms come together in designs for the physical world.
SPEC-TO-HARDWARE
Spec-to-Hardware is in development. This gallery shows engineering examples from our founder's work, including electronics, layouts and sensor assemblies. These support the workflow direction; they are separate from Ponchi AI product demonstrations. Open any image for a closer look.
FOUNDER PRIOR WORK
Explore the engineering work behind Spec-to-Real. These examples come from workflows our founder runs at UltraSense Systems, with design files, simulations, and tests that engineers can inspect and build on.
The EE agent checks its choices against a reference library of 174 real board designs. Examples include an eight-channel piezo transmit-and-receive board, four-layer development kits, sensor breakouts, regulator and op-amp test boards, a reworked haptic driver stage, and a multi-channel 3D-sonar board.
The analog agent sizes amplifier topologies from a five-transistor stage at 48 dB of gain to a folded cascode at 85 dB. Its phase margin matches Cadence Spectre to within a thousandth of a degree.
Original transistor-level schematic
Original frequency-response example
High-voltage driver · JSSC 2016, Fig. 8
Differential pixel front-end · JSSC 2016, Fig. 9
Receiver gain chain · JSSC 2016, Fig. 11
Demodulation and sample-and-hold · JSSC 2016, Fig. 14
A 36,000-cell design comes out placed and routed with zero routing violations, zero antenna nets, and positive setup and hold slack.
Examples include a tendon-driven robot finger, sensor evaluation cradles, test jigs, and development kit enclosures.
Original assembled CAD geometry
Original exploded components
Original recorded sensor traces and model
Firmware runs on a host with emulated peripherals and a real I²C link. Every recorded sensor capture is checked automatically against a Python reference model, channel by channel.
FOUNDER'S SILICON WORK
Our founder's UC Berkeley research joins ultrasonic transducers and a custom CMOS ASIC to image surface and subsurface fingerprint features. Explore the silicon and the echoes it captures.
IMAGING ASIC
SURFACE + SUBSURFACE
Schematic illustration
| Real finger | PDMS replica | |
|---|---|---|
| Surface | Real finger · surface | PDMS replica · surface |
| Inner layer | Real finger · inner layer | PDMS replica · inner layer |
Chip lead and inventor · UC Berkeley · 2012-2016
THE TECHNOLOGY
Model reasoning, bounded engineering tools and human review in one workflow. Explore the local requirements example and our founder's engineering methods.
You supply the goal, the sources, the authority, and what counts as done. The agent works inside that boundary and returns its result with the evidence attached. You delegate the task and keep the decision.
Agents draw on the company's own documents through retrieval rather than a model's memory, so every answer can point back to the source it came from — and several agents can work from the same ground truth.
The agent that does the work never signs it off. An independent reviewer, starting fresh, tests the result against the acceptance criteria, and the loop repeats until the findings stop.
Low-risk, reversible work runs with automatic checks. Work that is complex, costly to get wrong, or hard to undo gets broken down, independently reviewed, and released by a person.
IMPLEMENTATION SERVICES
Alongside product development, we provide AI consulting and implementation services. Start with an engineering workflow, connect the tools and knowledge it needs, and build a system your team can run and extend. Workshops, workflow assessment, focused builds, and training provide practical entry points.
A half-day or full-day session for leadership and the people who do the work. What today's AI tools and agents can actually do, shown live on your kind of work, and a short list of workflows worth trying first.
I sit with one team, map how a real piece of work moves from input to output, and mark where an agent can take a step, where a person must keep the decision, and what evidence would show it helped.
One bounded workflow, built end to end: the agent, its tools, the knowledge it reads, and the checks around it — running on your machines, against your own data, with your team reviewing every result.
The pilot becomes a working system your team owns. Standing instructions, shared memory, review loops, and the training that lets your people extend it without me.
HOW AN ENGAGEMENT RUNS
Start with the physical outcome you want to create. Each step produces engineering work you can inspect and a clear decision about the next step.
Define the physical goal
The chip, board, device, or object you want to create, with functional requirements and acceptance criteria.
01
Connect the tools and knowledge
Engineering software, reference designs, and project documents brought into a focused agent workflow.
02
Generate and verify the design
Agents produce design files and run checks, with engineers reviewing the outputs against the specification.
03
Prepare the build handoff
Organize the design outputs and verification results for the next engineering or fabrication step.
04
Integrate and train
Put the workflow in your team's hands, with instructions, review loops, and training to extend it.
05
A FATHER’S SIDE PROJECT · DRAW-TO-PLAY
Recorded demonstration. Between chips, circuit boards, and mechanical designs, Hao-Yen spends his days building hardware with AI. Then he saw his daughter’s drawing and wanted to do something simple: make her happy.
He built an agent workflow to bring her painted characters to life — carrying their own shapes and colours into 3D designs and little animations. That family moment became Draw-to-Play, a small side business with a warm purpose: helping a child see their imagination come alive.
ABOUT
Ponchi AI is an independent, early-stage AI venture founded by Hao-Yen Tang. We are developing engineering workflows for electronics teams, starting with requirements checks and traceable reports, alongside consulting and implementation work.
Company information
I'm Hao-Yen Tang, co-founder and CTO of UltraSense Systems, where I run chip, firmware, algorithm, and system engineering. I work on the same problem from both ends: the physics of a piezoelectric transducer, and the mixed-signal circuit that has to read it for microamps in a car door at minus forty degrees.
Before UltraSense I was a staff IC designer at TDK-InvenSense, where I was chip lead across several generations of the UltraPrint ultrasonic fingerprint sensor family. I did my PhD at UC Berkeley in Bernhard Boser's group, where the fingerprint sensor-on-a-chip I built became the prototype for that product line and won the 2016 ISSCC best paper award.
Over the past year I have put AI agents to work across my company's engineering — chip design, firmware, test, documentation — and learned what it takes for a team to trust what they produce. Through Ponchi AI, I develop Spec-to-Real AI services that connect specifications and designs to chips, boards, and physical objects. Alongside that product work, I help engineering teams build agent workflows and train the people who run them.
3,223
citations
29
h-index
36
granted US patents
Citation figures from Google Scholar, as of 2026-10-08.
Recognition
ISSCC BEST PAPER
Lewis Winner Award for Outstanding Paper
IEEE International Solid-State Circuits Conference, 2016 · for “3D Ultrasonic Fingerprint Sensor-on-a-Chip”
The chip in that paper became the prototype for a commercial ultrasonic fingerprint sensor product line.
3 papers at ISSCC
IEEE International Solid-State Circuits Conference, the venue where new chip designs are first presented
2014, 2015, 2016
Predoctoral Achievement Award
IEEE Solid-State Circuits Society
2015
Outstanding Student Paper Award
IEEE International Conference on Micro Electro Mechanical Systems
2017
CHIP PORTFOLIO
Explore Hao-Yen Tang's chip work across ultrasonic fingerprint imaging, touch and force sensing, medical ultrasound, and energy harvesting. Each program shows the device, his role, and the papers or patents behind it.
Piezoelectric micromachined ultrasonic transducers built monolithically on CMOS: the sensor, its analog front end, and an MCU on one die. The imaging chain reads a fingerprint through glass and metal by transmit beamforming and pulse-echo timing.
Chip lead, multiple generations · mixed-signal front end, high-voltage pulser, system bring-up
An ultrasound touch and force controller that turns an ordinary surface into a button. Sensor, analog front end, MCU, and the sensor-fusion algorithm all live on one chip, so a button can be placed behind metal with no hole and no moving part.
Chip lead · architecture, mixed-signal front end, high-voltage pulser, on-chip sensing algorithm
A multi-modal human-machine-interface SoC: capacitive touch, ultrasound touch and slider, and piezoelectric force sensing, fused on-chip. One part replaces the controller, the discrete force front ends, and the glue between them.
Chip lead · architecture, mixed-signal front end, high-voltage drive, sensor fusion
A controller that keeps a camera lens clear by driving it ultrasonically. One chip carries the power conversion from the vehicle battery, the piezo driver, an on-chip Hall-effect current sensor that tracks the transducer's resonance, and the digital control.
Chip lead · architecture, piezo driver, on-chip current sensing
A time-of-flight rangefinder on a chip, small enough and low-power enough to sit in a consumer device. Precision frequency demodulation and low-jitter time measurement are what make a centimetre-scale echo readable at microwatt power.
Analog designer, prototype and first production generation · high-voltage pulser, PLL and frequency demodulation, mixer and filter design
The thesis chip. A PMUT array bonded to CMOS that images a fingerprint in three dimensions, including the ridge structure below the skin surface. It became the prototype for a commercial fingerprint sensor product line.
Chip lead and inventor · array and circuit co-design, high-voltage pulser, beamforming
A handheld, battery-powered ultrasound imager demonstrated at ISSCC. The interesting part is the drive side: getting enough voltage into a discrete piezo element from a battery, efficiently enough that the whole instrument runs at milliwatts.
Chip lead · high-voltage drive, integrated charge pump
A millimetre-scale implant that records neural activity and is powered and read out by ultrasound through tissue, with no battery and no wire. I built the ASIC the prototype used; the work went on to seed iota Biosciences.
ASIC provider · ASIC design, ultrasound wireless power transfer
A DC-DC converter that starts up from 50 mV with no battery and no external kick, turning the few tens of millivolts a thermoelectric generator produces into a usable supply rail. My first silicon, and still my second most-cited paper.
Chip lead · converter architecture, startup circuit
A large-area ultrasonic fingerprint sensor built on a thin-film transistor backplane with a piezoelectric polymer film, driven by a companion ASIC.
Analog designer · high-voltage drive, transmit beamforming
CONTACT
Tell us your goal, what you have today, and the engineering workflow you want to improve. Whether it is a chip, a board, a device, or a creative object, email us to start the conversation.
info@ponchiai.comFounder on LinkedInGoogle ScholarGoogle Patents
